This invention relates generally to switching circuits, and more particularly, it relates to a complementary metal-oxide-semiconductor (CMOS) high voltage switch for interfacing between a decoder output and an input to an erasable, programmable read-only-memory (EPROM) wherein two separate signal paths are provided.
As is generally known, a high voltage is typically required when it is desired to program or write an EPROM cell and a low voltage is typically required when it is desired to read an EPROM cell. A conventional CMOS high voltage switch adapted for connection between a decoder output and an EPROM cell is illustrated in FIG. 1 of the drawings and has been labelled "Prior Art". This prior art switch suffers from the disadvantage that both the low voltage signal path and the high voltage signal path are through the same transistors; namely, P-channel MOS transistor P4 and N-channel MOS transistor N3. Due to the fact that these transistors are connected in series, their turn-on resistance values are relatively high. As a result, the operating speed of the switch is relatively slow. Further, during the low voltage operation the voltage at the output node 4 will be one threshold voltage drop below the supply potential VCC. Therefore, the full supply potential will not be obtainable at the output node without modifying the switch design to include intrinsic or depletion-mode type transistors. However, the increased processing cost in fabricating such transistors makes this design change unacceptable.
It would therefore be desirable to provide a high voltage switch implemented with all MOS transistors for providing a first signal path to accommodate a high voltage during a first or programming mode of operation and a second signal path to accommodate a low voltage during a second or read mode of operation, thereby increasing its speed of operation and improving latch-up immunity.